Semiconductor integrated circuit devices are built essentially in two dimensions. As the size of these devices continues to shrink, fundamental limitations on further size reductions are approached. An apt example is the capacitor in semiconductor memory devices. It has been reduced in size to the point where the charge capacity barely exceeds charge levels produced by noise mechanisms, e.g. alpha particle noise. It is inevitable that future devices will be constructed in three dimensions, opening a new horizon for microcircuit technology. One such approach has already been proposed and, in principle, built. See U.S. Pat. No. 4,353,086. See also IEEE Electron Device Letters, Vol. EDL-4, No. 11, November, 1983, Morie et al. The essence of the approach is to build the memory cell capacitor vertically into the substrate. This so-called trench or wall capacitor has a predominant portion of the storage plate extending into rather than along the chip surface. The amount of surface area consumed is only the area of the trench at the surface. For example, a simple trench capacitor 1.mu..times.4.mu..times.5.mu. (in depth) consumes 4.mu..sup.2 of chip surface area. The memory plate area available using the sidewalls of the trench is 5.mu..times.4.mu. per sidewall and 1.mu..times.5.mu. per endwall for a total of 50.mu..sup.2, or more than a tenfold increase in charge capacity over a 4.mu..sup.2 conventional memory plate with the same oxide thickness (neglecting the bottom of the trench). For a mesa type structure as described in the aforementioned patent, a 2.mu..times.2.mu..times.5.mu. mesa consumes 4.mu..sup.2 of chip area (neglecting isolation which in this structure is small) but provides a four walled capacitor area of 40.mu..sup.2.
The advantage of using vertical structures is obvious. However it is not obvious how to make them most effectively.
One ingredient that will be found in a variety of these kinds of structures, including that just described, is a vertical sidewall that is doped selectively with a conductivity type determining impurity in a controlled shallow region. "Doped selectively" is intended to describe an impurity region having an impurity level or kind different from the portion of the substrate into which the trench is formed. Doping such a sidewall by chemical diffusion from an impurity rich vapor is straightforward but does not afford the degree of control over the impurity level and distribution (including depth) that is required for many current devices. Doping a vertically extending sidewall by ion implantation, a process that normally does afford the desired shallow depth and controlled concentration, is difficult because the ion implanting beam is highly directional and does not effectively impact the sidewall.